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Digital Electronics

Introduction to Digitial Electronics
WHAT IS DIGITAL SIGNAL
DIGITAL ELECTRONICS
DIGITAL SIGNAL OVER ANALOG
ADVANTAGES OF DIGITAL SIGNAL
BINARY SYSTEM
BINARY NUMBER
BIT
BYTE
NUMBER SYSTEM
DECIMAL NUMBERS
BINARY NUMBERS
DECIMAL TO BINARY CONVERSION
BINARY TO DECIMAL CONVERSION
HEXADECIMAL TO DECIMAL
OCTAL TO DECIMAL
BINARY ARITHMETIC OPERATIONS
BINARY ADDITION
BINARY SUBTRACTION
BINARY MULTIPLICATION
BINARY DIVISION
BINARY COMPLIMENTS
1’S COMPLIMENT
2’S COMPLIMENT
ADDITION USING 1’S COMPLIMENT
SUBTRACTION USING 1’S COMPLIMENT
9’s compliments
10’s compliment
R’S COMPLIMENTS
(R-1)’S COMPLIMENTS
BOOLEAN ALGEBRA
INTRODUCTION
BOOLEAN ALGEBRA OPERATIONS
BOOLEAN ALGEBRA TERMINOLOGIES
LAWS OF BOOLEAN ALGEBRA
DE MORGAN’S THEOREM
DE MORGAN’S FIRST LAW
DE MORGAN’S FIRST LAW
MINIMISATION TECHNIQUE
TRUTH TABLE
CANONICAL MINTERM
CANONICAL MAXTERM
SOLVED EXAMPLE
KARNAUGH MAP
2 VARIABLE K-MAP
3 VARIABLE K-MAP
4 VARIABLE K-MAP
5 VARIABLE K-MAP
LOGIC GATES
INTRODUCTION
AND GATE
OR GATE
NOT GATE
NAND GATE
NOR GATE
XOR GATE
X-NOR GATE
DIGITAL LOGIC FAMILY
INTRODUCTION
DIODE TRANSISTOR LOGIC
RESISTOR TRANSISTOR LOGIC
3 INPUT RTL NOR GATE
TRANSISTOR TRANSISTOR LOGIC
CHARACTERSTICS OF DIGITAL LOGIC FAMILY
FAN IN FAN OUT
POWER DISSIPATION
FIGURE OF MERIT
EMITTER COUPLED LOGIC
ARITHMATIC OPERATIONS
HALF ADDER
FULL ADDER
HALF SUBTRACTOR
FULL SUBTRACTOR
PARALLEL BINARY SUBTRACTOR
DERIVING FULL SUBTRACTOR
DIFFERENT BINARY CODES
INTRODUCTION
WEIGHTED BINARY SYSTEMS
8421 CODE OR BCD CODE
2421 CODE
5211 CODE
REFLECTIVE CODE
SEQUENTIAL CODE
EXCESS 3 CODE
EXCESS 3 CODE EXAMPLE
GRAY CODE
MORSE CODE CHART
COMBINATIONAL CIRCUITS
MULTIPLEXER
4 TO 1 MULTIPLEXER
APPLICATIONS OF MULTIPLEXER
DEMULTIPLEXER
1 TO 4 DEMUX
APPLICATIONS OF DEMUX
ENCODERS
INTRODUCTION
PRIORITY ENCODER
8 TO 3 PRIORITY ENCODER
4 TO 2 PRIORITY ENCODER
DECODERS
INTRODUCTION
BASIC BINARY DECODER
CASCADING DECODERS
APPLICATION OF DECODER
PARITY GENERATORS
PARITY BIT
PARITY GENERATOR
EVEN PARITY GENERATOR
ODD PARITY GENERATOR
EVEN PARITY CHECKER
ODD PARITY CHECKER
FLIP FLOP
INTRODUCTION
S-R FLIP FLOP
D FLIP FLOP
J-K FLIP FLOP
T FLIP FLOP
SHIFT REGISTERS
INTRODUCTION
SERIAL IN SERIAL OUT SHIFT REGISTER
SERIAL IN PARALLEL OUT
PARALLEL IN PARALLEL OUT
BIDIRECTIONAL SHIFT REGISTER
COUNTERS IN SHIFT REGISTER
COUNTERS
COUNTERS
SYNCHRONOUS COUNTERS
4 BIT SYNCHRONOUS UP COUNTERS
4 BIT SYNCHRONOUS UP COUNTER OPERATION
4 BIT SYNCHRONOUS DOWN COUNTER
APPLICATION OF SYNCHRONOUS COUNTERS
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PARALLEL IN PARALLEL OUT

PARALLEL IN SERIAL OUT

This shift register allows parallel input and generates a serial output, so this is known as Parallel in Serial out (PISO) Shift Register.

The Parallel in Serial out (PISO) Shift Register circuit is shown above. This circuit can be built with four D-flip-flops, where the CLK signal is connected directly to all the FFs. However, the input data is connected separately to every FF using a multiplexer at every FF’s input.

The earlier FF output, as well as parallel data input, is connected toward the multiplexer’s input & multiplexer’s output can be connected to the second flip flop. Once the same CLK signal is given to every flip flop, then all the flip flops will be synchronous with each other. The applications of these registers include converting parallel data to the serial data.