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Digital Electronics

Introduction to Digitial Electronics
WHAT IS DIGITAL SIGNAL
DIGITAL ELECTRONICS
DIGITAL SIGNAL OVER ANALOG
ADVANTAGES OF DIGITAL SIGNAL
BINARY SYSTEM
BINARY NUMBER
BIT
BYTE
NUMBER SYSTEM
DECIMAL NUMBERS
BINARY NUMBERS
DECIMAL TO BINARY CONVERSION
BINARY TO DECIMAL CONVERSION
HEXADECIMAL TO DECIMAL
OCTAL TO DECIMAL
BINARY ARITHMETIC OPERATIONS
BINARY ADDITION
BINARY SUBTRACTION
BINARY MULTIPLICATION
BINARY DIVISION
BINARY COMPLIMENTS
1’S COMPLIMENT
2’S COMPLIMENT
ADDITION USING 1’S COMPLIMENT
SUBTRACTION USING 1’S COMPLIMENT
9’s compliments
10’s compliment
R’S COMPLIMENTS
(R-1)’S COMPLIMENTS
BOOLEAN ALGEBRA
INTRODUCTION
BOOLEAN ALGEBRA OPERATIONS
BOOLEAN ALGEBRA TERMINOLOGIES
LAWS OF BOOLEAN ALGEBRA
DE MORGAN’S THEOREM
DE MORGAN’S FIRST LAW
DE MORGAN’S FIRST LAW
MINIMISATION TECHNIQUE
TRUTH TABLE
CANONICAL MINTERM
CANONICAL MAXTERM
SOLVED EXAMPLE
KARNAUGH MAP
2 VARIABLE K-MAP
3 VARIABLE K-MAP
4 VARIABLE K-MAP
5 VARIABLE K-MAP
LOGIC GATES
INTRODUCTION
AND GATE
OR GATE
NOT GATE
NAND GATE
NOR GATE
XOR GATE
X-NOR GATE
DIGITAL LOGIC FAMILY
INTRODUCTION
DIODE TRANSISTOR LOGIC
RESISTOR TRANSISTOR LOGIC
3 INPUT RTL NOR GATE
TRANSISTOR TRANSISTOR LOGIC
CHARACTERSTICS OF DIGITAL LOGIC FAMILY
FAN IN FAN OUT
POWER DISSIPATION
FIGURE OF MERIT
EMITTER COUPLED LOGIC
ARITHMATIC OPERATIONS
HALF ADDER
FULL ADDER
HALF SUBTRACTOR
FULL SUBTRACTOR
PARALLEL BINARY SUBTRACTOR
DERIVING FULL SUBTRACTOR
DIFFERENT BINARY CODES
INTRODUCTION
WEIGHTED BINARY SYSTEMS
8421 CODE OR BCD CODE
2421 CODE
5211 CODE
REFLECTIVE CODE
SEQUENTIAL CODE
EXCESS 3 CODE
EXCESS 3 CODE EXAMPLE
GRAY CODE
MORSE CODE CHART
COMBINATIONAL CIRCUITS
MULTIPLEXER
4 TO 1 MULTIPLEXER
APPLICATIONS OF MULTIPLEXER
DEMULTIPLEXER
1 TO 4 DEMUX
APPLICATIONS OF DEMUX
ENCODERS
INTRODUCTION
PRIORITY ENCODER
8 TO 3 PRIORITY ENCODER
4 TO 2 PRIORITY ENCODER
DECODERS
INTRODUCTION
BASIC BINARY DECODER
CASCADING DECODERS
APPLICATION OF DECODER
PARITY GENERATORS
PARITY BIT
PARITY GENERATOR
EVEN PARITY GENERATOR
ODD PARITY GENERATOR
EVEN PARITY CHECKER
ODD PARITY CHECKER
FLIP FLOP
INTRODUCTION
S-R FLIP FLOP
D FLIP FLOP
J-K FLIP FLOP
T FLIP FLOP
SHIFT REGISTERS
INTRODUCTION
SERIAL IN SERIAL OUT SHIFT REGISTER
SERIAL IN PARALLEL OUT
PARALLEL IN PARALLEL OUT
BIDIRECTIONAL SHIFT REGISTER
COUNTERS IN SHIFT REGISTER
COUNTERS
COUNTERS
SYNCHRONOUS COUNTERS
4 BIT SYNCHRONOUS UP COUNTERS
4 BIT SYNCHRONOUS UP COUNTER OPERATION
4 BIT SYNCHRONOUS DOWN COUNTER
APPLICATION OF SYNCHRONOUS COUNTERS
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4 BIT SYNCHRONOUS UP COUNTERS

4 BIT SYNCHRONOUS UP COUNTERS

The 4 bit up counter is designed by using JK flip flop. External clock pulse is connected to all the flip flops in parallel.

For designing the counters JK flip flop is preferred .The significance of using JK flip flop is that it can toggle its state if both the inputs are high, depending on the clock pulse.

The inputs of first flip flop  are connected to HIGH (logic 1), which makes the flip flop to toggle, for every clock pulse entered into it. So the synchronous counter will work with single clock signal and changes its state with each pulse.

The output of first JK flip flop (Q) is connected to the input of second flip flop. The AND gates (which are connected externally) drives the inputs of other two flip flops . The inputs of these AND gates , are supplied from previous stage lip flop outputs.

 

If inputs of FF2 are connected directly to the Q1 output of FF1 , the counter would not function properly. This is because , the Q1 value is high at count of 210 , this means that the FF2 flip flop will toggle for the 3rd clock pulse. This results in wrong counting operation, gives the count as 710 instead of 410.

 

To prevent this problem AND gates are used at the input side of FF2 and FF3. The output of the AND gate will be high only when the Q0, Q1 outputs are high. So for the next clock pulse, the count will be 00012.

 

Similarly, the flip flop FF3 will toggle for the fourth clock pulse when Q0, Q1 and Q2 are high. The Q3 output will not toggle till the 8th clock pulse and will again remain high until 16th clock pulse. After the 16th clock pulse, the q outputs of all flip flops will return to 0.