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Digital Electronics

Introduction to Digitial Electronics
WHAT IS DIGITAL SIGNAL
DIGITAL ELECTRONICS
DIGITAL SIGNAL OVER ANALOG
ADVANTAGES OF DIGITAL SIGNAL
BINARY SYSTEM
BINARY NUMBER
BIT
BYTE
NUMBER SYSTEM
DECIMAL NUMBERS
BINARY NUMBERS
DECIMAL TO BINARY CONVERSION
BINARY TO DECIMAL CONVERSION
HEXADECIMAL TO DECIMAL
OCTAL TO DECIMAL
BINARY ARITHMETIC OPERATIONS
BINARY ADDITION
BINARY SUBTRACTION
BINARY MULTIPLICATION
BINARY DIVISION
BINARY COMPLIMENTS
1’S COMPLIMENT
2’S COMPLIMENT
ADDITION USING 1’S COMPLIMENT
SUBTRACTION USING 1’S COMPLIMENT
9’s compliments
10’s compliment
R’S COMPLIMENTS
(R-1)’S COMPLIMENTS
BOOLEAN ALGEBRA
INTRODUCTION
BOOLEAN ALGEBRA OPERATIONS
BOOLEAN ALGEBRA TERMINOLOGIES
LAWS OF BOOLEAN ALGEBRA
DE MORGAN’S THEOREM
DE MORGAN’S FIRST LAW
DE MORGAN’S FIRST LAW
MINIMISATION TECHNIQUE
TRUTH TABLE
CANONICAL MINTERM
CANONICAL MAXTERM
SOLVED EXAMPLE
KARNAUGH MAP
2 VARIABLE K-MAP
3 VARIABLE K-MAP
4 VARIABLE K-MAP
5 VARIABLE K-MAP
LOGIC GATES
INTRODUCTION
AND GATE
OR GATE
NOT GATE
NAND GATE
NOR GATE
XOR GATE
X-NOR GATE
DIGITAL LOGIC FAMILY
INTRODUCTION
DIODE TRANSISTOR LOGIC
RESISTOR TRANSISTOR LOGIC
3 INPUT RTL NOR GATE
TRANSISTOR TRANSISTOR LOGIC
CHARACTERSTICS OF DIGITAL LOGIC FAMILY
FAN IN FAN OUT
POWER DISSIPATION
FIGURE OF MERIT
EMITTER COUPLED LOGIC
ARITHMATIC OPERATIONS
HALF ADDER
FULL ADDER
HALF SUBTRACTOR
FULL SUBTRACTOR
PARALLEL BINARY SUBTRACTOR
DERIVING FULL SUBTRACTOR
DIFFERENT BINARY CODES
INTRODUCTION
WEIGHTED BINARY SYSTEMS
8421 CODE OR BCD CODE
2421 CODE
5211 CODE
REFLECTIVE CODE
SEQUENTIAL CODE
EXCESS 3 CODE
EXCESS 3 CODE EXAMPLE
GRAY CODE
MORSE CODE CHART
COMBINATIONAL CIRCUITS
MULTIPLEXER
4 TO 1 MULTIPLEXER
APPLICATIONS OF MULTIPLEXER
DEMULTIPLEXER
1 TO 4 DEMUX
APPLICATIONS OF DEMUX
ENCODERS
INTRODUCTION
PRIORITY ENCODER
8 TO 3 PRIORITY ENCODER
4 TO 2 PRIORITY ENCODER
DECODERS
INTRODUCTION
BASIC BINARY DECODER
CASCADING DECODERS
APPLICATION OF DECODER
PARITY GENERATORS
PARITY BIT
PARITY GENERATOR
EVEN PARITY GENERATOR
ODD PARITY GENERATOR
EVEN PARITY CHECKER
ODD PARITY CHECKER
FLIP FLOP
INTRODUCTION
S-R FLIP FLOP
D FLIP FLOP
J-K FLIP FLOP
T FLIP FLOP
SHIFT REGISTERS
INTRODUCTION
SERIAL IN SERIAL OUT SHIFT REGISTER
SERIAL IN PARALLEL OUT
PARALLEL IN PARALLEL OUT
BIDIRECTIONAL SHIFT REGISTER
COUNTERS IN SHIFT REGISTER
COUNTERS
COUNTERS
SYNCHRONOUS COUNTERS
4 BIT SYNCHRONOUS UP COUNTERS
4 BIT SYNCHRONOUS UP COUNTER OPERATION
4 BIT SYNCHRONOUS DOWN COUNTER
APPLICATION OF SYNCHRONOUS COUNTERS
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BASIC BINARY DECODER

2 TO 4 BINARY DECODER

The 2 to 4 binary decoder has 2 binary inputs and 4 coded outputs. The block diagram and circuit diagram is shown below. A and B are the two inputs and the output produced is one of the minterms the two inputs.

The circuit diagram has two inverters, which will provide the complement of two inputs A and B. Each AND gates generates one of the minters as an output.

When Enable(EN) is set at logic 1, one of the outputs(Y0, Y1, Y2, Y3) will be active for a given input. The remaining outputs will be logic 0.

From the above truth table, the operation can be understood. When both the inputs A and B are 0, Y0 will be at active HIGH or logic 1 and the remaining output pins are active LOW or logic 0.

Similarly, output pin Y1 will be at logic 1 for A = 0 and B = 1. The coded output for the inputs A = 1 and B = 1 is ‘1000’, where Y3 pin is at logic 1 and the remaining pins are at logic 0.