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Digital Electronics

Introduction to Digitial Electronics
WHAT IS DIGITAL SIGNAL
DIGITAL ELECTRONICS
DIGITAL SIGNAL OVER ANALOG
ADVANTAGES OF DIGITAL SIGNAL
BINARY SYSTEM
BINARY NUMBER
BIT
BYTE
NUMBER SYSTEM
DECIMAL NUMBERS
BINARY NUMBERS
DECIMAL TO BINARY CONVERSION
BINARY TO DECIMAL CONVERSION
HEXADECIMAL TO DECIMAL
OCTAL TO DECIMAL
BINARY ARITHMETIC OPERATIONS
BINARY ADDITION
BINARY SUBTRACTION
BINARY MULTIPLICATION
BINARY DIVISION
BINARY COMPLIMENTS
1’S COMPLIMENT
2’S COMPLIMENT
ADDITION USING 1’S COMPLIMENT
SUBTRACTION USING 1’S COMPLIMENT
9’s compliments
10’s compliment
R’S COMPLIMENTS
(R-1)’S COMPLIMENTS
BOOLEAN ALGEBRA
INTRODUCTION
BOOLEAN ALGEBRA OPERATIONS
BOOLEAN ALGEBRA TERMINOLOGIES
LAWS OF BOOLEAN ALGEBRA
DE MORGAN’S THEOREM
DE MORGAN’S FIRST LAW
DE MORGAN’S FIRST LAW
MINIMISATION TECHNIQUE
TRUTH TABLE
CANONICAL MINTERM
CANONICAL MAXTERM
SOLVED EXAMPLE
KARNAUGH MAP
2 VARIABLE K-MAP
3 VARIABLE K-MAP
4 VARIABLE K-MAP
5 VARIABLE K-MAP
LOGIC GATES
INTRODUCTION
AND GATE
OR GATE
NOT GATE
NAND GATE
NOR GATE
XOR GATE
X-NOR GATE
DIGITAL LOGIC FAMILY
INTRODUCTION
DIODE TRANSISTOR LOGIC
RESISTOR TRANSISTOR LOGIC
3 INPUT RTL NOR GATE
TRANSISTOR TRANSISTOR LOGIC
CHARACTERSTICS OF DIGITAL LOGIC FAMILY
FAN IN FAN OUT
POWER DISSIPATION
FIGURE OF MERIT
EMITTER COUPLED LOGIC
ARITHMATIC OPERATIONS
HALF ADDER
FULL ADDER
HALF SUBTRACTOR
FULL SUBTRACTOR
PARALLEL BINARY SUBTRACTOR
DERIVING FULL SUBTRACTOR
DIFFERENT BINARY CODES
INTRODUCTION
WEIGHTED BINARY SYSTEMS
8421 CODE OR BCD CODE
2421 CODE
5211 CODE
REFLECTIVE CODE
SEQUENTIAL CODE
EXCESS 3 CODE
EXCESS 3 CODE EXAMPLE
GRAY CODE
MORSE CODE CHART
COMBINATIONAL CIRCUITS
MULTIPLEXER
4 TO 1 MULTIPLEXER
APPLICATIONS OF MULTIPLEXER
DEMULTIPLEXER
1 TO 4 DEMUX
APPLICATIONS OF DEMUX
ENCODERS
INTRODUCTION
PRIORITY ENCODER
8 TO 3 PRIORITY ENCODER
4 TO 2 PRIORITY ENCODER
DECODERS
INTRODUCTION
BASIC BINARY DECODER
CASCADING DECODERS
APPLICATION OF DECODER
PARITY GENERATORS
PARITY BIT
PARITY GENERATOR
EVEN PARITY GENERATOR
ODD PARITY GENERATOR
EVEN PARITY CHECKER
ODD PARITY CHECKER
FLIP FLOP
INTRODUCTION
S-R FLIP FLOP
D FLIP FLOP
J-K FLIP FLOP
T FLIP FLOP
SHIFT REGISTERS
INTRODUCTION
SERIAL IN SERIAL OUT SHIFT REGISTER
SERIAL IN PARALLEL OUT
PARALLEL IN PARALLEL OUT
BIDIRECTIONAL SHIFT REGISTER
COUNTERS IN SHIFT REGISTER
COUNTERS
COUNTERS
SYNCHRONOUS COUNTERS
4 BIT SYNCHRONOUS UP COUNTERS
4 BIT SYNCHRONOUS UP COUNTER OPERATION
4 BIT SYNCHRONOUS DOWN COUNTER
APPLICATION OF SYNCHRONOUS COUNTERS
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1 TO 4 DEMUX

1 TO 4 DEMUX

The 1-to-4 demultiplexer has 1 input bit, 2 control or select bits, and 4 output bits. An example of 1-to-4 demultiplexer is IC 74155. The 1-to-4 demultiplexer is shown in figure below-

The input bit is labelled as Data D. This data bit is transmitted to the selected output lines, which depends on the values of A and B, the control or Select Inputs.

When  A B = 0 1 , the second AND gate from the top is enabled while other AND gates are disabled. Therefore, data bit D is transmitted to the output Y1, giving Y1 = Data.

If D is LOW, Y1 is LOW. If D is HIGH, Y1 is HIGH. The value of Y1 depends upon the value of D. All other outputs are in low state.

If the control input is changed to  A B = 1 0 , all the gates are disabled except the third AND gate from the top. Then, D is transmitted only to the Y2 output, and Y2 = Data.